1. Field of the Invention
The present invention relates to a level shift circuit, which is applied to a non-volatile semiconductor memory device such as a NAND-type flash memory.
2. Description of the Related Art
In a NAND-type flash memory, various voltages are applied to optimize the program characteristic and read characteristic. For example, in a data read operation, voltage VREAD is applied as a read voltage to a word line selected by a row decoder. The gate of a transfer transistor supplied with the read voltage VREAD is supplied with a voltage VREADH higher than the voltage VREAD. Thus, the transfer transistor can transfer the voltage VREAD.
Conventionally, the voltage VREAD has been about 6 V. However, a memory storing multi-level data such as 8 levels and 16 levels in one memory cell has been recently developed. This kind of memory requires about 8 V as a voltage VREAD. Because, the storing the multi-level data requires a level threshold distribution higher than the conventional memory storing binary and four-level data. For this reason, the voltage VREAD must be stepped up according to high level threshold distribution. Moreover, it is effective to improve the voltage VREAD in order to prevent back pattern dependency (i.e., influence of an extent of threshold distribution generated by data written in other non-select memory cell of the same NAND string).
If the voltage VREAD is set as 8 V, a voltage VREADH becomes about 10 V. These voltages VREAD and VREADH are supplied to desired circuits using a cross-coupled level shift circuit. The cross-coupled level shift circuit is a circuit, which has a small layout area and operates at high speed. Thus, the level shift circuit is used for various portions of a NAND-type flash memory. For example, the level shift circuit is used as the following various circuits. One is a driving circuit for driving the foregoing word line of row system and a select gate. Another is a circuit for make control to delay a rise speed when a bit line is charged. Another is a driving circuit of cell source and well.
A level shifter has been developed as this kind of level shift circuit (e.g., see Jpn. Pat. Appln. KOKAI Publications No. H10-41806, and H7-74616). In this level shift circuit, a gate of a P-channel MOS transistor (hereinafter, referred to as a PMOS) serial-connected to a cross-coupled circuit is supplied with a fixed bias. A back gate and a source are connected.
However, it is difficult to use the conventional cross-coupled level shift circuit if the voltage VREAD becomes 10 V. This results from the following reason. A high-voltage P-channel MOS transistor (HVP transistor) forming the level shift circuit has the following problem. Specifically, a voltage which can be applied between drain and source, and between drain and well is 8 V. If a voltage exceeding 8 V is applied, breakdown failure occurs. In order to improve the breakdown voltage of transistors, ion implantation is additionally required, for example. This is a factor of make high a process cost. Therefore, it is desired to provide a level shift circuit, which can prevent a circuit area from increasing, and improve a breakdown voltage.